The Automated Test Blog

OK, time for the last of my 5 trends in test for 2008:

Emulation-Based ATE That Improves System-on-a-Chip and System-in-a-Package Testing

As semiconductor devices become more complex, the process of testing each part completely with a traditional vector-based methodology is increasingly difficult. Complex systems-on-a-chip(SoCs) and systems-in-a-package (SiPs) require a system-level functional test more closely related to testing components placed on a printed circuit board than a typical chip test, but they still require the high speeds demanded in production test for the semiconductor industry. The strategy of testing a device by emulating actual real-world signals provides a better method of functional test for these types of high-speed systems. This emulation-based ATE, or also termed “Protocol-Aware ATE” during last year’s International Test Conference, combines FPGA-based hardware to emulate the rest of the system in real-time with the pin electronics found in traditional ATE. This lowers the total cost of test through better use-case coverage and improves the user’s ability to debug failures. I explained this idea in more detail in a recent blog post. In 2008, I expect more vendors to incorporate elements of emulation-based tests into traditional tester architectures and for more users to incoproate platforms currently used in functional test, such as PXI, into chip validation and test applications.

As I stated in an earlier blog post, I’m planning to discuss one of five industry trends per blog entry over the next few weeks. My 3^rd trend is:

Growing Popularity of FPGA-Enabled Instrumentation
Another area experiencing rapid expansion in the test industry is the increase in system-level tools for field-programmable gate arrays (FPGAs). FPGAs are powerful because they are inherently parallel, deterministic, and reliable and can be defined and reconfigured in software. While FPGAs are used inside many embedded designs, and even standalone instruments, users are not typically given access to reprogram them. More manufacturers are beginning to include open FPGAs on modular instruments and are giving test engineers the means in software to reprogram them according to their requirements. With this capability, test engineers can embed a custom algorithm into the device to perform in-line processing inside the FPGA or emulate part of the system that requires a real-time response. Historically, most test engineers do not have expertise to program FPGAs because they familiarity with hardware description languages like Verilog or VHDL which use low-level syntax to describe hardware behavior. New system-level tools are emerging that provide test engineers with the ability to rapidly configure FPGAs without writing low-level HDL code. LabVIEW, for example, can target onboard FPGAs and synthesize the necessary hardware directly from a graphical LabVIEW program, dramatically reducing the complexity of the code development. I’ve been amazed at the things our customers, who are often domain exprerts, but not experts in hardware design, have been able to accomplish with LabVIEW FPGA.  Examples include testing RFID devices performing bit-error-rate testing (BERT) of military communication protocols.

I recently presented at a group called the Semiconductor Test Consortium, or STC. There were two subjects of the talk – learnings from PXI and other industry standards and emerging trends in SOC (System On a Chip) and SIP (System In a Package) functional testing. The latter has been the subject of some interesting discussion of late in the semiconductor test industry.

The challenge that many chip designers face is that the devices are increasing in complexity at a rate that exceeds the advances in testing technology. The result is that the cost to manufacturer complex semiconductor devices is decreasing faster than the cost to test them. In validation, the issue is not only test cost, but overall test time, which can impact the time to validate new silicon and, ultimately, time to market.

As devices begin to resemble complete systems, a higher level test methodology is called for to both reduce the tester’s complexity, as well as provide a tighter link back to the system level design tools. An engineer at Broadcom recently coined the term “Protocol Aware ATE” to describe this need and at the International Test Conference (ITC) this year, there was a panel discussion on this trend. The idea is to create a test system that can perform functional testing of a device by emulating the device in situ, or in its intended surroundings. This requires the capability to model the other components of the system and to interact with the device in real time.

This is similar in many was to functional testing that is already routinely done at the board and system levels. For some devices, this is just stimulus-response type testing performed at the end of the manufacturing process. When real-time response is needed, this is very similar to a technique called Hardware in the Loop, or HIL, used extensively in automotive and aerospace validation testing. For chip testing, the real time requirements are often more stringent. A technology that has promise to meet many of these requirements is the Field Programmable Gate Array (FGPA), also noted as an ideal architecture in the Broadcom paper. A programmable FPGA placed in the tester close to the device under test, can be used to emulate the system and test the device in situ. The FPGA also holds promise as a target that can run system models directly from system level design tools to bring design and test closer together.