The Automated Test Blog

I was recently invited to give a talk at the VLSI Test Symposium titled “Migration of PXI Instruments into Semiconductor Test“. The session focused on emerging trends in semiconductor ATE and on work that is currently going on in both vendors consortia, to migrate PXI into semiconductor test applications. The presentation covered the key challenges currently facing engineers that are validating and testing increasingly complex devices such as SoCs and SiPs. As I previously blogged, Protocol Aware ATE is a new technique for testing these complex devices at a system level. In the presentation, I also covered existing work to build semiconductor ATE based on PXI, including examples of augmenting existing ATE, creating testers with a PXI measurement core, and work by the Semiconductor Test Consortium on a Portable Test Instrument Module, or PTIM. The PTIM initiative is designed to provide a way to add ancillary measurement capability to existing ATE platforms. The STC has been evaluating various options and has the desire to standardize PTIM on an exiting industry standard. PXI has been proposed as the PTIM platform and is currently being discussed at the Global STC Conference this week in San Diego. This proposal will enable ATE customers and vendors to leverage the large commercial investment in PXI and extend ATE capability by using the 1500 existing PXI modules currently available.

OK, time for the last of my 5 trends in test for 2008:

Emulation-Based ATE That Improves System-on-a-Chip and System-in-a-Package Testing

As semiconductor devices become more complex, the process of testing each part completely with a traditional vector-based methodology is increasingly difficult. Complex systems-on-a-chip(SoCs) and systems-in-a-package (SiPs) require a system-level functional test more closely related to testing components placed on a printed circuit board than a typical chip test, but they still require the high speeds demanded in production test for the semiconductor industry. The strategy of testing a device by emulating actual real-world signals provides a better method of functional test for these types of high-speed systems. This emulation-based ATE, or also termed “Protocol-Aware ATE” during last year’s International Test Conference, combines FPGA-based hardware to emulate the rest of the system in real-time with the pin electronics found in traditional ATE. This lowers the total cost of test through better use-case coverage and improves the user’s ability to debug failures. I explained this idea in more detail in a recent blog post. In 2008, I expect more vendors to incorporate elements of emulation-based tests into traditional tester architectures and for more users to incoproate platforms currently used in functional test, such as PXI, into chip validation and test applications.

I recently presented at a group called the Semiconductor Test Consortium, or STC. There were two subjects of the talk – learnings from PXI and other industry standards and emerging trends in SOC (System On a Chip) and SIP (System In a Package) functional testing. The latter has been the subject of some interesting discussion of late in the semiconductor test industry.

The challenge that many chip designers face is that the devices are increasing in complexity at a rate that exceeds the advances in testing technology. The result is that the cost to manufacturer complex semiconductor devices is decreasing faster than the cost to test them. In validation, the issue is not only test cost, but overall test time, which can impact the time to validate new silicon and, ultimately, time to market.

As devices begin to resemble complete systems, a higher level test methodology is called for to both reduce the tester’s complexity, as well as provide a tighter link back to the system level design tools. An engineer at Broadcom recently coined the term “Protocol Aware ATE” to describe this need and at the International Test Conference (ITC) this year, there was a panel discussion on this trend. The idea is to create a test system that can perform functional testing of a device by emulating the device in situ, or in its intended surroundings. This requires the capability to model the other components of the system and to interact with the device in real time.

This is similar in many was to functional testing that is already routinely done at the board and system levels. For some devices, this is just stimulus-response type testing performed at the end of the manufacturing process. When real-time response is needed, this is very similar to a technique called Hardware in the Loop, or HIL, used extensively in automotive and aerospace validation testing. For chip testing, the real time requirements are often more stringent. A technology that has promise to meet many of these requirements is the Field Programmable Gate Array (FGPA), also noted as an ideal architecture in the Broadcom paper. A programmable FPGA placed in the tester close to the device under test, can be used to emulate the system and test the device in situ. The FPGA also holds promise as a target that can run system models directly from system level design tools to bring design and test closer together.