The Automated Test Blog

As recently discussed in a post by Rick Nelson of Test and Measurement World magazine, the Semiconductor Test Consortium (STC) has begun work on defining a Portable Test Instrument Module (PTIM) - a standard plug-in module for performing ancillary measurements on existing semiconductor ATE.  My colleague, Luke Schreier, delivered a presentation at the last STC global meeting that was very well-received which proposed PXI as a suitable specification to build from.   The business case is very compelling - traditional ATE architectures are built to accommodate the densest and highest speed test pins possible - 1 kilowatt of power per board is not uncommon.  This is necessary for the high speed digital electronics needed to test the latest processors, for instance.  When you need to add some audio or RF measurements into the system, however, the infrastructure can be overkill.  Moreover, to fully integrate an instrument into a tester requires expertise of the ATE vendor, so to make these measurements, the vendor may be required to invest significantly in development of measuement functionality already available on the open market, just in other form factors.

It is interesting to me that the semiconductor test industry is recognizing some of the features we designed into the original PXI specification.  In fact, one of the slides we used to use in the early days of PXI showed a set of rack and stack instruments on one side and a “big iron” semiconductor tester on the other, with PXI right in the middle.  The point was that PXI borrowedconcepts from both of these markets - the measurement quality from box instruments, and the card modular form factor and integrated timing and synchronization from semiconductor ATE.  It looks like after 10 years, its finally come full circle.

I recently presented at a group called the Semiconductor Test Consortium, or STC. There were two subjects of the talk – learnings from PXI and other industry standards and emerging trends in SOC (System On a Chip) and SIP (System In a Package) functional testing. The latter has been the subject of some interesting discussion of late in the semiconductor test industry.

The challenge that many chip designers face is that the devices are increasing in complexity at a rate that exceeds the advances in testing technology. The result is that the cost to manufacturer complex semiconductor devices is decreasing faster than the cost to test them. In validation, the issue is not only test cost, but overall test time, which can impact the time to validate new silicon and, ultimately, time to market.

As devices begin to resemble complete systems, a higher level test methodology is called for to both reduce the tester’s complexity, as well as provide a tighter link back to the system level design tools. An engineer at Broadcom recently coined the term “Protocol Aware ATE” to describe this need and at the International Test Conference (ITC) this year, there was a panel discussion on this trend. The idea is to create a test system that can perform functional testing of a device by emulating the device in situ, or in its intended surroundings. This requires the capability to model the other components of the system and to interact with the device in real time.

This is similar in many was to functional testing that is already routinely done at the board and system levels. For some devices, this is just stimulus-response type testing performed at the end of the manufacturing process. When real-time response is needed, this is very similar to a technique called Hardware in the Loop, or HIL, used extensively in automotive and aerospace validation testing. For chip testing, the real time requirements are often more stringent. A technology that has promise to meet many of these requirements is the Field Programmable Gate Array (FGPA), also noted as an ideal architecture in the Broadcom paper. A programmable FPGA placed in the tester close to the device under test, can be used to emulate the system and test the device in situ. The FPGA also holds promise as a target that can run system models directly from system level design tools to bring design and test closer together.